Conventional techniques may be used to accurately recover a clock signal from a pair of synchronized differential data signals (DATA and /DATA) provided onto a data bus by an upstream integrated circuit device. However, accurate clock synchronization can be more difficult to achieve when multiple out-of-phase clock signals are recovered from corresponding pairs of data signals having different relative timing skews. This is particularly true for high speed devices requiring accurate and aggressive (i.e., early) phasing of a high speed internal core clock used to synchronize a large number of data signals having potentially significantly different timing skews. One such high speed device is an advanced memory buffer (AMB), which may be used in fully-buffered DIMM modules. As known to those skilled in the art, the AMB may be configured to receive as many as ten (10) lanes of serialized data at 4.0-Gbps or higher data rates before deserializing and deskewing operations are performed on the data. A conventional technique to achieve internal core clock synchronization with deserialized and deskewed data includes generating an internal clock signal that is always synchronized with the deserialized data having a worst skew characteristic (i.e., greatest lagging skew relative to an earliest lane of data). Unfortunately, such a conventional synchronization technique may not be sufficiently aggressive for devices operating at the highest required rates of operation because no adjustment can be made to the phase of the generated internal clock signal.